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EL5162, EL5163, EL5262, EL5263, EL5362
Data Sheet January 4, 2008 FN7388.10
500MHz Low Power Current Feedback Amplifiers with Enable
The EL5162, EL5163, EL5262, EL5263, and EL5362 are current feedback amplifiers with a bandwidth of 500MHz. This makes these amplifiers ideal for today's high speed video and monitor applications. With a supply current of just 1.5mA and the ability to run from a single supply voltage from 5V to 12V, these amplifiers are also ideal for handheld, portable or battery-powered equipment. The EL5162 also incorporates an enable and disable function to reduce the supply current to 100A typical per amplifier. Allowing the CE pin to float or applying a low logic level will enable the amplifier. The EL5162 is available in 6 Ld SOT-23 and 8 Ld SOIC packages, the EL5163 in 5 Ld SOT-23 and SC-70 packages, the EL5262 in the 10 Ld MSOP package, the EL5263 in 8 Ld MSOP and SO packages, and the EL5362 in 16 Ld SOIC (0.150") and QSOP packages. All operate over the industrial temperature range of -40C to +85C.
Features
* 500MHz to 3dB bandwidth * 4000V/s slew rate * 1.5mA supply current * Single and dual supply operation, from 5V to 12V supply span * Fast enable/disable (EL5162, EL5262 and EL5362 only) * Available in SOT-23 packages * Pb-free available (RoHS compliant) * High speed, 1.4GHz product available (EL5167 and EL5167) * High speed, 4mA, 630MHz product available (EL5164 and EL5165)
Applications
* Battery-powered equipment * Handheld, portable devices * Video amplifiers * Cable drivers * RGB amplifiers * Test equipment * Instrumentation * Current to voltage converters
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2007, 2008. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
EL5162, EL5163, EL5262, EL5263, EL5362 Ordering Information
PART NUMBER EL5162IS EL5162IS-T7* EL5162IS-T13* EL5162ISZ (Note) EL5162ISZ-T7* (Note) EL5162ISZ-T13* (Note) EL5162IW-T7* EL5162IW-T7A* EL5162IWZ-T7* (Note) EL5162IWZ-T7A* (Note) EL5163IW-T7* EL5163IW-T7A* EL5163IWZ-T7* (Note) EL5163IWZ-T7A* (Note) EL5163IC-T7* EL5163IC-T7A* EL5163ICZ-T7* (Note) EL5163ICZ-T7A* (Note) EL5262IY EL5262IY-T7* EL5262IY-T13* EL5262IYZ (Note) EL5262IYZ-T7* (Note) EL5262IYZ-T13* (Note) EL5263IS EL5263IS-T7* EL5263IS-T13* EL5263ISZ (Note) EL5263ISZ-T7* (Note) EL5263ISZ-T13* (Note) EL5263IY EL5263IY-T7* EL5263IY-T13* EL5263IYZ (Note) EL5263IYZ-T7* (Note) EL5263IYZ-T13* (Note) EL5362IS EL5362IS-T7* EL5362IS-T13* PART MARKING 5162IS 5162IS 5162IS 5162ISZ 5162ISZ 5162ISZ j j BAKA BAKA d d BALA BALA E E BDA BDA BLAAA BLAAA BLAAA BBTAA BBTAA BBTAA 5263IS 5263IS 5263IS 5263ISZ 5263ISZ 5263ISZ BMAAA BMAAA BMAAA BBBJA BBBJA BBBJA EL5362IS EL5362IS EL5362IS 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 6 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 (Pb-free) 6 Ld SOT-23 (Pb-free) 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 (Pb-free) 5 Ld SOT-23 (Pb-free) 5 Ld SC-70 (1.25mm) 5 Ld SC-70 (1.25mm) 5 Ld SC-70 (1.25mm) (Pb-free) 5 Ld SC-70 (1.25mm) (Pb-free) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) 10 Ld MSOP (3.0mm) (Pb-free) 10 Ld MSOP (3.0mm) (Pb-free) 10 Ld MSOP (3.0mm) (Pb-free) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld SOIC (150 mil) (Pb-free) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) 8 Ld MSOP (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) (Pb-free) 8 Ld MSOP (3.0mm) (Pb-free) 16 Ld SOIC (150 mil) 16 Ld SOIC (150 mil) 16 Ld SOIC (150 mil) PACKAGE PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0038 MDP0038 MDP0038 MDP0038 MDP0038 MDP0038 MDP0038 MDP0038 P5.049 P5.049 P5.049 P5.049 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0027 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0027 MDP0027 MDP0027
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Ordering Information
PART NUMBER EL5362ISZ (Note) EL5362ISZ-T7* (Note) EL5362ISZ-T13* (Note) EL5362IU EL5362IU-T7* EL5362IU-T13* EL5362IUZ (Note) EL5362IUZ-T7* (Note) EL5362IUZ-T13* (Note) (Continued) PART MARKING EL5362ISZ EL5362ISZ EL5362ISZ 5362IU 5362IU 5362IU 5362IUZ 5362IUZ 5362IUZ PACKAGE 16 Ld SOIC (150 mil) (Pb-free) 16 Ld SOIC (150 mil) (Pb-free) 16 Ld SOIC (150 mil) (Pb-free) 16 Ld QSOP (150 mil) 16 Ld QSOP (150 mil) 16 Ld QSOP (150 mil) 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) 16 Ld QSOP (Pb-free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040 MDP0040
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Pinouts
EL5162 (8 LD SOIC) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 + 8 CE 7 VS+ 6 OUT 5 NC OUT 1 VS- 2 IN+ 3
EL5162 (6 LD SOT-23) TOP VIEW
6 VS+ 5 CE 4 IN-
EL5163 (5 LD SOT-23, SC-70) TOP VIEW
OUT 1 VS- 2 +IN+ 3 4 IN5 VS+
+-
EL5262 (10 LD MSOP) TOP VIEW
OUT 1 IN- 2 IN+ 3 VS- 4 CE 5 + + 10 VS+ 9 OUT 8 IN7 IN+ 6 CE
EL5263 (8 LD SOIC, MSOP) TOP VIEW
OUT1 1 IN- 2 IN+ 3 VS- 4 + + 8 VS+ 7 OUT2 6 IN5 IN+
EL5362 (16 LD SOIC, QSOP) TOP VIEW
INA+ 1 CEA 2 VS- 3 CEB 4 INB+ 5 NC 6 CEC 7 INC+ 8 + + + 16 INA15 OUTA 14 VS+ 13 OUTB 12 INB11 NC 10 OUTC 9 INC-
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . 13.2V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . . 50mA Slewrate of VS+ to VS-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/s Maximum Voltage between IN+ and IN-, disabled . . . . . . . . . . 1.5V Current into IN+, IN-, CE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW -3dB Bandwidth
VS+ = +5V, VS- = -5V, RF = 750 for AV = 1, RF = 400 for AV = 2, RL = 150, TA = +25C unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
AV = +1, RL = 500, RF = 598 AV = +2, RL = 150, RF = 422
500 233 30
MHz MHz MHz 4000 6000 V/s V/s ns nV/Hz pA/Hz pA/Hz %
BW1 SR
0.1dB Bandwidth Slew Rate VO = -2.5V to +2.5V, AV = +2, RL = 100 (EL5262, EL5263, EL5362) VO = -2.5V to +2.5V, AV = +2, RL = 100 (EL5162, EL5163) 2000 2800
2500 4000 25 3 10 6.5
tS eN iNiN+ dG dP
0.1% Settling Time Input Voltage Noise IN- Input Current Noise IN+ Input Current Noise Differential Gain Error (Note 1) Differential Phase Error (Note 1)
VOUT = -2.5V to +2.5V, AV = +1
AV = +2 AV = +2
0.05 0.15
DC PERFORMANCE VOS TCVOS ROL Offset Voltage Input Offset Voltage Temperature Coefficient Transimpedance Measured from TMIN to TMAX 500 -5 1.5 6 1000 +5 mV V/C k
INPUT CHARACTERISTICS CMIR CMRR -ICMR +IIN -IIN RIN CIN Common Mode Input Range Common Mode Rejection Ratio - Input Current Common Mode Rejection + Input Current - Input Current Input Resistance Input Capacitance Guaranteed by CMRR test VIN = 3V 3 50 -1 -8 -10 0.8 3.3 62 0.22 0.5 2 1.6 1 75 +1 +8 +10 3 V dB A/V A A M pF
OUTPUT CHARACTERISTICS VO Output Voltage Swing RL = 150 to GND RL = 1k to GND IOUT Output Current RL = 10 to GND 3.35 3.75 60 3.6 3.9 100 3.75 4.15 V V mA
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362
Electrical Specifications
PARAMETER SUPPLY ISON ISOFFISOFF+ PSRR -IPSR Power Supply Rejection Ratio - Input Current Power Supply Rejection DC, VS = 4.75V to 5.25V DC, VS = 4.75V to 5.25V Supply Current - Enabled, per Amplifier Supply Current - Disabled, per Amplifier No load, VIN = 0V No load, VIN = 0V 1.3 -25 0 65 -0.5 1.5 -14 10 76 0.1 +0.5 2.0 0 +25 mA A A dB A/V VS+ = +5V, VS- = -5V, RF = 750 for AV = 1, RF = 400 for AV = 2, RL = 150, TA = +25C unless otherwise specified. (Continued) CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
ENABLE (EL5162, EL5262, EL5362 ONLY) tEN tDIS IIHCE IILCE VIHCE VILCE NOTE: 1. Standard NTSC test, AC signal amplitude = 286mVP-P, f = 3.58MHz Enable Time Disable Time CE Pin Input High Current CE Pin Input Low Current CE Input High Voltage for Power-down CE Input Low Voltage for Power-down CE = VS+ CE = (VS+) -5V 1 -1 VS+ - 1 VS+ - 3 380 800 5 0 25 +1 ns ns A A V V
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves
+4 +3 NORMALIZED GAIN (dB) +2 +1 0 -1 -2 -3 -4 -5 -6 100k 1M 10M 100M 1G VCC = +5V VEE = -5V RL = 500 RF = 598 +4 +3 NORMALIZED GAIN (dB) +2 +1 0 -1 -2 -3 -4 -5 -6 100k 1M 10M 100M FREQUENCY (Hz) 1G VCC = +5V VEE = -5V RF = 375
FREQENCY (Hz)
FIGURE 1. FREQUENCY RESPONSE FOR AV = +1
FIGURE 2. FREQUENCY RESPONSE FOR AV = +4.6
+2 +1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 -1 -2 -3 -4 -5 -6 -7 VCC = +5V VEE = -5V AV = +10 RL = 150 RF = 375 1M 10M FREQUENCY (Hz) 100M 1G
+3 +2 +1 0 -1 -2 -3 -4 -5 -6 VCC = +5V VEE = -5V RL = 150 RF = 422 1M 10M FREQUENCY (Hz) 100M 1G
-8 100k
-7 100k
FIGURE 3. FREQUENCY RESPONSE FOR AV = +10
FIGURE 4. FREQUENCY RESPONSE FOR AV = +2
+3 +2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) +1 0 -1 -2 -3 -4 -5 -6 -7 100k VCC = +5V VEE = -5V RL = 150 RF = 422 1M 10M FREQUENCY (Hz) 100M 1G
+5 +4 +3 +2 +1 0 -1 -2 -3 -4 -5 100k 1M 10M 100M 500M VCC, VEE = 5V 4V 3V 2.5V 6V AV = +1 RL = 150 RF = 698
FREQUENCY (Hz)
FIGURE 5. FREQUENCY RESPONSE FOR AV = +4
FIGURE 6. FREQUENCY RESPONSE FOR VARIOUS VCC, VEE
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves
100 OUTPUT IMPEDANCE () VCC = +5V VEE = -5V AV = +2 10 VCC = +5V VEE = -5V AV = +2 RL = 150 INPUT RISE TIME 1.028ns
(Continued)
1V/DIV
1
OUTPUT RISE TIME 2.218ns
2V/DIV
0.1 10k 100k 1M FREQUENCY (Hz) 10M 100M 4ns/DIV
FIGURE 7. CLOSED LOOP OUTPUT IMPEDANCE
FIGURE 8. EL5262 OUTPUT RISE TIME
1V/DIV
INPUT FALL TIME 1.036ns
VCC = +5V VEE = -5V AV = +2 RL = 150
CH 1
OUTPUT FALL TIME 2.21ns
2V/DIV CH 2 CH1 = 5V CH2 = 200mV M = 100ns 4ns/DIV 100ns/DIV
FIGURE 9. EL5262 OUTPUT FALL TIME
FIGURE 10. TURN ON TIME
CH1 = 5V CH2 = 200mV M = 100ns PSRR (dB) CH1
0 VCC = +5V -10 V = -5V EE -20 AV = +2 RL = 150 -30 -40 -50 -60 -70
CH2
-80 -90 -100 100 100ns/DIV 1k 10k 100k 1M 10M 100M FREQUENCY (Hz)
FIGURE 11. TURN OFF TIME
FIGURE 12. PSRR (VCC)
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves
VCC = +5V -10 VEE = -5V -20 AV = +2 RL = 150 -30 PSRR (dB) -40 -50 -60 -70 -80 -90 -100 100 1k 10k 100k 1M 10M 100M 0
(Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) 1.2 1.250W 1.0 0.8 909mW 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SO8 JA = +110C/W SO16 (0.150") JA = +80C/W
FREQUENCY (Hz)
FIGURE 13. PSRR (VEE)
FIGURE 14. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1.0 893mW 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QSOP16 JA = +112C/W 0.50
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.45 435mW 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5/6 JA = +230C/W
FIGURE 15. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 16. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.0 0.9 870mW POWER DISSIPATION (W) POWER DISSIPATION (W) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) MSOP8/10 JA = +115C/W 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
909mW
SO16 (0.15 0") JA = +110C/W
625mW SO8 JA = +160C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 17. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Typical Performance Curves
1.2 POWER DISSIPATION (W) 1.0 0.8 633mW 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) QSOP16 JA = +158C/W POWER DISSIPATION (W)
(Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5/6 JA = +256C/W 391mW
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 20. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.6 POWER DISSIPATION (W) 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 AMBIENT TEMPERATURE (C) 486mW MSOP8/10 JA = +206C/W
FIGURE 21. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Small Outline Transistor Plastic Packages (SC70-5)
D
P5.049
VIEW C
e1
5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS MIN 0.80 0.00 0.80 0.15 0.15 0.08 0.08 1.85 1.80 1.15 MAX 1.10 0.10 1.00 0.30 0.25 0.22 0.20 2.15 2.40 1.35 6 6 3 3 4 5 0.25 Rev. 3 7/07 NOTES SYMBOL A MIN 0.031 0.000 0.031 0.006 0.006 0.003 0.003 0.073 0.071 0.045 MAX 0.043 0.004 0.039 0.012 0.010 0.009 0.009 0.085 0.094 0.053
5 E 1 2 3
4 C L C L E1
A1 A2 b b1 c c1
C
e
C L 0.20 (0.008) M C L C
b
D E E1
A
A2
A1
SEATING PLANE -C-
e e1 L L1
0.0256 Ref 0.0512 Ref 0.010 0.018 0.017 Ref. 0.006 BSC 0o 5 0.004 0.004 0.010 8o
0.65 Ref 1.30 Ref 0.26 0.46 0.420 Ref. 0.15 BSC 0o 5 0.10 0.15 8o
0.10 (0.004) C
L2
WITH PLATING c
b b1 c1
N R R1 NOTES:
BASE METAL
1. Dimensioning and tolerances per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO-203AA. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs.
4X 1 R1 R GAUGE PLANE SEATING PLANE L C 4X 1 VIEW C 0.4mm L1
4. Footlength L measured at reference to gauge plane. 5. "N" is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only.
L2
0.75mm
2.1mm
0.65mm TYPICAL RECOMMENDED LAND PATTERN
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FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY MILLIMETERS SYMBOL A A1 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. D 2/07 NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included.
E
E1
PIN #1 I.D.
A2 b c
B
1 (N/2)
D E E1
e C SEATING PLANE 0.10 C N LEADS b
H
e L L1 N
0.08 M C A B
L1 A c SEE DETAIL "X"
2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
14
FN7388.10 January 4, 2008
EL5162, EL5163, EL5262, EL5263, EL5362 Quarter Size Outline Plastic Packages Family (QSOP)
A D N (N/2)+1
MDP0040
QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY INCHES SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES
PIN #1 I.D. MARK
A A1 A2 b
0.068 0.006 0.056 0.010 0.008 0.193 0.236 0.154 0.025 0.025 0.041 16
0.068 0.006 0.056 0.010 0.008 0.341 0.236 0.154 0.025 0.025 0.041 24
0.068 0.006 0.056 0.010 0.008 0.390 0.236 0.154 0.025 0.025 0.041 28
Max. 0.002 0.004 0.002 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference
1, 3 2, 3 Rev. F 2/07
E
E1
1 B 0.010 CAB
(N/2)
c D E
e C SEATING PLANE 0.004 C 0.007 CAB b
H
E1 e L L1 N
L1 A c SEE DETAIL "X"
NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994.
0.010 A2 GAUGE PLANE L 44 DETAIL X
A1
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 15
FN7388.10 January 4, 2008

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